[25p-P11-1~16] 13.7 Compound and power devices, process technology and characterization

[25p-P11-5] Examination of reduction of GaN/SiO₂ hole traps by suppressing the formation of interfacial oxide layer

〇Tsurugi Kondo¹, Katsunori Ueno¹, Ryo Tanaka¹, Shinya Takashima¹, Masaharu Edo¹ (1.Fuji Electric)

Keywords:semiconductor, MOS Interface

Suppression of Ga-O bond at interface is effective method predicted by first principle calculation for reduction of GaN/SiO₂ hole traps. It has also reported that interface with low hole traps was realized on high p-type concentration layer. Therefore we extracted SiO₂ deposition method for suppressing formation of interfacial oxide layer, prepared MOS capacitors combined with various p-type concentration layer and conducted C-V measurement. We report about observed influences of interfacial oxide layer and p-type concentration on hole traps.