[C-3/4] 光エレクトロニクス/レーザ・量子エレクトロニクス

[C-3/4-20] Wafer- and chip-level characterization of photonic integrated circuits by cascaded grating-couplers and spot-size converters

^○Moataz Eissa¹, Ryuya Sasaki¹, Tsuyoshi Horikawa¹, Tomohiro Amemiya¹, Nobuhiko Nishiyama² (1.Tokyo Tech, 2.Tokyo Tech)

Keywords:Silicon Photonics

Wafer-level testing is crucial reduce the cost of silicon photonic integrated circuits. However, to proceed to wafer-level testing, utilization of grating couplers (GCs) is needed, which have relatively large loss compared with edge coupling structures using spot-size converters. Therefore, wafer-level testing is usually performed only for a test element group (TEG) pattern. In this work, we would like to propose the structure with both GCs and SSCs in same device to realize a wafer-level testing to estimate the characteristics of final chip-level devices. Good agreement between wafer- and chip-level measurments of was obtained.