[C-5-3] Heavily-Doped Poly-Si Gate and Epi-First Source/Drain Extension Technique in Strained Si Nanowire MOSFETs with Reduced Papasitic Resistance
Y. Nakabayashi1, M. Saitoh1, T. Ishihara1, T. Numata1, K. Uchida2, J. Koga1
(1.Toshiba Corp., 2.Tokyo Inst. of Tech. , Japan)
https://doi.org/10.7567/SSDM.2010.C-5-3