Session information

Oral Presentation

12: Advanced Circuits / Systems Interacting with Innovative Devices and Materials

[K-5] Advanced Neuron and AI Systems

Wed. Sep 28, 2022 10:45 AM - 12:00 PM 304 (3F)

Session Chair: Takeshi Yoshida (Hiroshima Univ.), Yitao Ma (Tohoku Univ.)

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10:45 AM - 11:15 AM

[K-5-01 (Invited)] Hiddenite: CNN Inference Accelerator for Randomly Weighted Neural Networks

〇Jaehoon Yu¹, Kazutoshi Hirose¹, Kota Ando¹, Yasuyuki Okoshi¹, Angel Lopez Garcia-Arias¹, Junnosuke Suzuki¹, Thiem Van Chu¹, Kazushi Kawamura¹, Masato Motomura¹ (1. Tokyo Ins. of Tech. (Japan))

Presentation style: On-site (in-person)

11:15 AM - 11:30 AM

[K-5-02] A 1.2nJ/Classification 2.4mm² Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18µm CMOS

〇Rei Sumikawa¹, Kota Shiba¹, Atsutake Kosuge¹, Mototsugu Hamada¹, Tadahiro Kuroda¹ (1. Univ. of Tokyo (Japan))

Presentation style: Online

11:30 AM - 11:45 AM

[K-5-03] Neutron-induced stuck error bits and their recovery in DRAMs on GPU cards

〇Masanori Hashimoto¹, Yangchao Zhang², Kojiro Ito² (1. Kyoto Univ. (Japan), 2. Osaka Univ. (Japan))

Presentation style: On-site (in-person)

11:45 AM - 12:00 PM

[K-5-04] Design of an Energy-Efficient Nonvolatile Lookup Table Circuit Using Active-Load-Localized Circuitry with Self-Terminated Writing/Reading

〇Daisuke Suzuki¹, Takahiro Hanyu² (1. The University of Aizu (Japan), 2. Tohoku University (Japan))

Presentation style: On-site (in-person)

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Session information

[K-5] Advanced Neuron and AI Systems

[K-5-01 (Invited)] Hiddenite: CNN Inference Accelerator for Randomly Weighted Neural Networks

[K-5-02] A 1.2nJ/Classification 2.4mm2 Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18µm CMOS

[K-5-03] Neutron-induced stuck error bits and their recovery in DRAMs on GPU cards

[K-5-04] Design of an Energy-Efficient Nonvolatile Lookup Table Circuit Using Active-Load-Localized Circuitry with Self-Terminated Writing/Reading

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[K-5-02] A 1.2nJ/Classification 2.4mm² Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18µm CMOS