[E-4] Oxide Semiconductors for Logic and Memory Applications

[E-4-05] 3D monolithic CAAC-IGZO/Si hybrid CMOS ring oscillator and 64 multiple states high efficient (>200TOPS/W) for Analog Memory Computing

〇Min-Cheng Chen¹, Satoru Ohshita², Hidefumi Rikimaru², Yoshiyuki Kurokawa², Satoshi Watanabe², Yuki Imoto², Yoshinori Ando², Shang-Shiug Chuang¹, Hiroshi Yoshida¹, Ming-Han Liao³, Shou-Zen Chang¹, Shunpei Yamazaki² (1. Powerchip Semiconductor Manufacturing Corp. (Taiwan), 2. Semiconductor Energy Laboratory Co., Ltd. (Japan), 3. National Taiwan University (Taiwan))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.E-4-05

We present a CAAC-IGZO/Si hybrid CMOS technology with monolithic 3D stacked high stability MIM/OS-FET in Si BEOL process. The insert OS-LSI process shows no impact on Si FEOL characteristic performance. A 51-stages CAAC-IGZO/Si hybrid CMOS ring oscillator capable of reducing 20% layout area has been successfully demonstrated. On the other hand, the CAAC-IGZO/Si Analog in-Memory Computing (AiMC) chip also achieves a multiple weighting states of 64, an operation efficiency of more than 200TOPS/W, and an inference accuracy larger than 90% (MNIST). We believe it is suitable for applications of decrypt encryption and/or IoT sensors.