2D transistor top and bottom gate stack scaling in 300mm pilot line

Quentin Smets

doi:https://doi.org/10.7567/SSDM.2022.F-10-05

Presentation information

Oral Presentation

Focus Session 2 (Area1&2&8)

[F-10] CMOS and Memory Applications of Low Dimensional Materials II

Thu. Sep 29, 2022 4:00 PM - 5:45 PM 201 (2F)

Session Chair: Takamasa Kawanago (Tokyo Tech), Sakura Takeda (NAIST)

5:15 PM - 5:45 PM

[F-10-05 (Invited)] 2D transistor top and bottom gate stack scaling in 300mm pilot line

〇Quentin Smets¹, Tom Schram¹, Daire Cott¹, Anish Dangol¹, Dennis Lin¹, Souvik Ghosh¹, Rudy Verheyen¹, Steven Brems¹, Benjamin Groven¹, Pierre Morin¹, Inge Asselberghs¹, Gouri Sankar Kar¹ (1. imec (Belgium))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.F-10-05

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