[F-6] Charge-Based Memory Devices for AI Applications

[F-6-01] CMOS-compatible Charge-trap Transistors with Engineered Tunnel-barrier for Artificial Synaptic Electronics

〇KI-WOONG PARK¹, Won-Ju Cho¹ (1. Univ. of Kwangwoon (Korea))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.F-6-01

In this study, we proposed the silicon-on-insulator (SOI)-based charge-trap synaptic transistors with engineered tunnel barrier. The charge-trap transistors with mature CMOS-compatible technology can gradually and stably modulate channel conductance through the charge trapping layer and electron tunneling. The engineered charge trapping layer realized artificial synaptic operation by emulating the excitatory post-synaptic current (EPSC) response and long-term potentiation/depression behaviors for multiple gate stimulation. In addition, the charge-trap transistors reliable mimicked the synaptic operation even at a high temperature of 125 oC. As a result, we proposed the in-memory computing possibility for artificial neural network systems with charge-trap synaptic transistors.