[G-1] Cryo-CMOS

[G-1-04] Accurate Evaluation of Interface Trap Density at InAs MOS Interfaces by Using C-V characteristics at Low Temperatures

〇Ryohei Yoshizu¹, Kei Sumita¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1. Univ. of Tokyo (Japan))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.G-1-04

A method of accurately evaluating the interface trap density (Dit) by using the high-frequency C-V curves at InAs MOS interfaces is experimentally examined. Low-temperature measurements are performed to suppress the response of interface states. We study the impacts of the accuracy of the oxide capacitance, the distribution function, and the C-V hysteresis due to slow traps on Dit evaluated by the high-frequency C-V (Terman) method. It is found that temperatures lower than 40 K and the C-V measurements in limited voltage ranges are indispensable in the accurate evaluation of Dit.