[G-10] Advanced CMOS: Device, Process and Material

[G-10-03] Investigation of access resistance components in Si-channel p-FinFET using cascaded devices.

〇Pierre Eyben¹, Goutham Arutchelvan¹, Thomas Chiarella¹, Hiroaki Arimura¹, Romain Ritzenthaler¹, Jérome Mitard¹, Eugenio Dentoni Litta ¹, Naoto Horiguchi¹, Ludovic Goux¹ (1. Imec (Belgium))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.G-10-03

Within this work, a new procedure is proposed to split and analyze the different access resistance compo-nents for Si-channel p-FinFET devices. This is realized combining a dedicated cascaded FET test-structure and advanced data filtering procedures. This is allowing us to identify the relative weight of contact, epi, interface and channel resistance components and hence to propose strategies to minimize the total access resistance such as the introduction of graded SiGe source-drain epi.