[G-3] Quantum Computing I

[G-3-02] Introduction of deep impurity levels of S and Zn and high temperature single-electron transport in Si tunnel FETs

〇Yoshisuke Ban¹, Kimihiko Kato², Shota Iizuka², Shigenori Murakami², Koji Ishibashi¹, Satoshi Moriyama³, Takahiro Mori², Keiji Ono¹ (1. RIKEN (Japan), 2. AIST (Japan), 3. Tokyo Denki Univ. (Japan))

Presentation style:

https://doi.org/10.7567/SSDM.2022.G-3-02

We introduced deep impurity levels with strong electron confinement into Si devices for high temperature operation of Si qubit and observed single-electron transport through the deep levels. First, Group II-VI impurities, S and Zn, were introduced into the Si substrate by ion implantation as deep impurities, and post-implantation annealing condition was found from the depth profiles of S and Zn measured by SIMS. Next, the formation of deep levels in Si was confirmed by DLTS analyses. Then, we performed the process integration into Si devices under the S and Zn I/I condition found in the above experiments. To realize single-electron transport through deep impurity levels, we employed a single-electron transistor with a tunnel FET structure. Finally, as a result of the evaluation of S and Zn implanted Si TFETs, large charging energy values were observed at 10 K and 300 K. These values are 10 - 20 times higher than room temperature, suggesting high temperature stability as a Si qubit.