[G-3] Quantum Computing I

[G-3-03] Device Structure and Fabrication Process for MOS Type Silicon Spin Qubit Realizing Process-Variation-Robust two-Qubit SWAP Gate

〇Hidehiro Asai¹, Shota Iizuka¹, Tohru Mogami¹, Junichi Hattori¹, Koichi Fukuda¹, Tsutomu Ikegami¹, Kimihiko Kato¹, Hiroshi Oka¹, Takahiro Mori¹ (1. National Institute of Advanced Industrial Science and Technology (AIST) (Japan))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.G-3-03

In this study, we propose a device structure, gate fabrication process, and back-bias-assisted operation for Si spin qubits, to realize high robustness of two-qubit SWAP gate operation against process variations. For the first time, we present a novel qubit design for 6σ yield SWAP gate operation with 99% fidelity assuming device size fluctuation of the IRDS target for 2022. These technologies provide a solution to complete a universal quantum gate set realizing universal quantum computers with silicon.