[H-2] Novel Function Devices

[H-2-04] The impact of floating gate insertion regarding channel percolation of ferroelectric FET

〇Sangho Lee¹, Giuk Kim¹, Taehyong Eom¹, Sanghun Jeon¹ (1. Korea Advanced Institute of Science and Technology (KAIST) (Korea))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.H-2-04

As the scaling of ferroelectric FET (FeFET) progresses, channel percolation caused by random distribution of the ferroelectric film's crystal phase has been recognized as a primary issue. We investigated a structural approach to minimize device-to-device variance and performance degradation due to spatial variations of crystal phase, which worsens with the scaling of FeFETs, using technol-ogy computer-aided design (TCAD) simulations. By in-serting a floating gate below the ferroelectric film, the influence of ferroelectric polarization on the lower chan-nel can be averaged, thus reducing device variation sig-nificantly. At the same time, it results in a larger MW of FeFETs and a significant improvement in accuracy of in-memory computing applications. We believe that a floating gate insertion will be a key structural strategy for enhancing FeFET reliability.