[J-6] Interface Technologies

[J-6-01] Improvement of Channel Mobility in AlSiO/GaN MOSFETs using Thin Interfacial Layers to Reduce Border Traps

〇Kenji Ito¹, Kazuyoshi Tomita², Daigo Kikuta¹, Masahiro Horita², Tetsuo Narita¹ (1. Toyota Central R&D Labs., Inc. (Japan), 2. Nagoya Univ. (Japan))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.J-6-01

The improvement of channel mobility for AlSiO/p-type GaN-based metal-oxide-semiconductor field-effect transistors (MOSFETs) were demonstrated. By inserting thin AlN interfacial layer (IL) at the oxide-semiconductor interface, the hysteresis in transfer characteristic was reduced and the channel mobility was improved to around 100 cm2/Vs. The interfacial layer was oxidized after post-deposition annealing (PDA) and disappeared. The results suggest the interfacial layer suppress the reaction at the AlSiO/GaN interface during PDA, resulting in reducing the border traps.