[J-6] Interface Technologies

[J-6-02] Suppression of GaO_x interlayer growth towards stable SiO₂/GaN MOS devices

〇Kentaro Onishi¹, Takuma Kobayashi¹, Hidetoshi Mizobata¹, Mikito Nozaki¹, Akitaka Yoshigoe², Takayoshi Shimura¹, Heiji Watanabe¹ (1. Osaka Univ. (Japan), 2. JAEA (Japan))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.J-6-02

Although a growth of GaOx interlayer at the SiO2/GaN interface improves the MOS interface properties, a recent study suggested that the GaOx interlayer is easily reduced during the annealing process, inducing positive fixed charge at the interface. In the present study, we formed SiO2 by sputter deposition to minimize the growth of unstable GaOx interlayer. With post-deposition annealing (PDA) at 800°C, SiO2/GaN MOS structure with a small C-V hysteresis was obtained. Furthermore, the negative shift of VFB during the annealing was suppressed, thanks to the minimization of GaOx interlayer formaiton.