[J-6] Interface Technologies

[J-6-03] Characterization of Trap States of SiO₂/GaN Interface and SiO₂ Layer by Deep Level Transient Spectroscopy

〇Shingo Ogawa¹, Hidetoshi Mizobata², Takuma Kobayashi², Takayoshi Shimura², Heiji Watanabe² (1. Toray Research Center (Japan), 2. Osaka Univ. (Japan))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.J-6-03

The interface trap states and the oxide trap states of the SiO2/GaN MOS capacitors were investigated using DLTS. The energy distribution of the trap states were estimated and as a result, the dispersed oxide trap states at around 0.2 eV and 0.8 eV from the conduction band minimum of GaN were confirmed for the capacitor without the thermal annealing. The interface state density was proven to decrease to around 1e10 cm-2eV-1 by the thermal annealing.