[K-1] 3D Integration and Advanced Packaging I

[K-1-01] Simulation and Experimental Study of Stretchable 3D Corrugated Interconnections for Chiplet-Embedded Flexible Hybrid Electronics Using Wafer-Level Packaging

〇CHANG LIU¹, Yuki Susumago¹, Tadaaki Hoshi¹, Hisashi Kino², Tetsu Tanaka^1,2, Takafumi Fukushima^1,2 (1. Graduate School of Eng., Tohoku Univ. (Japan), 2. Graduate School of Biomed. Eng., Tohoku Univ. (Japan))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.K-1-01

The bendability and stretchability of inter-chip wires are one of the important issues for FHE (Flexible Hybrid Electronics). Being bent with a small bending radius (R smaller than 1 mm) or in-plane stretched with critical deformation (strain larger than 1%) leads to high stress concentration in the wires, causing electric disconnection and structural failure such as delamination with high possibility. This work deals with vertically corrugated interconnections compatible to advanced FOWLP (fan-out wafer-level packaging)-based FHE we have developed so far. The out-of-plane geometric structure is simulated to reduce mechanical stress and the validity of the optimized 3D design is experimentally evaluated to verify the simulational analyses.