[K-1] 3D Integration and Advanced Packaging I

[K-1-02] Warpage and Stress Study of Wafer-to-Wafer Bonding Fabrication Process

〇Wei FENG¹, Haruo Shimamoto¹, Tsuyoshi Kawagoe², Ichirou Honma², Masato Yamasaki², Fumitake Okutsu², Takatoshi Masuda², Katsuya Kikuchi¹ (1. National Inst. of Advanced Indus. Sci. and Tech. (AIST) (Japan), 2. UltraMemory Inc. (Japan))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.K-1-02

Wafer warpage causes alignment issues and the degradation of the device’s performance. The increase of metal layers in the stack direction in the development of devices will worsen the warpage problem. We successfully study the warpage issue in Wafer-to-Wafer (W2W) bonding process with experiments and full wafer simulation. After the W2W bonding process, the wafer warpage increases to 3 times the single wafer warpage value. The simulation model is validated by the good agreement with the measured data. The wafer-level stress is revealed in the W2W bonding process. With the validated model, the wafer warpage of the 4-stack wafer bonding is estimated to be 7 times the single wafer warpage value.
This study provides useful information on wafer warpage and stress in the W2W bonding process and reveals the severe warpage issue with increasing the stacked metal layers.