[K-7] Advanced Systems with Innovative Devices

[K-7-03] Feasibility Study for 32-level cell using Memory with 13.5-V 0.5-um OSFET Monolithically Stacked on 13.5-V 1.6-um CMOSFET

〇Hiroki Inoue¹, Shoki Miyata¹, Yusuke Komura¹, Yuki Okamoto¹, Takanori Matsuzaki¹, Hidetomo Kobayashi¹, Yoshinori Ando¹, Hitoshi Kunitake¹, Yoshiyuki Kurokawa¹, Shunpei Yamazaki¹ (1. Semiconductor Energy Laboratory Co., Ltd. (Japan))

Presentation style: On-site (in-person)

https://doi.org/10.7567/SSDM.2022.K-7-03

We found a possibility to achieve a 32-level cell using a 16-level-cell memory test chip in which a 13.5-V 0.5-um crystalline oxide semiconductor field-effect transistor (OSFET) was monolithically stacked on a 13.5-V 1.6-um CMOSFET. The variation in a read 16-level analog voltage, the +/-3 sigma range, was 0.202 V at a maximum. With regard to retention characteristics, 16-level data was retained for three hours at room temperature, and the voltage change was 0.038 V at a maximum. The narrowest difference between distributions was 0.253 V. The maximum +/-3 sigma range was smaller than the narrowest difference between distributions, which shows a possibility that one more piece data is able to be retained between pieces of data.