A Low Power 8 Bit Parallel A/D Converter with High Accuracy Process

T. Takemoto; M. Inoue; H. Sadamatsu; A. Matsuzawa; Y. Hirofuji; T. Komeda

doi:https://doi.org/10.7567/SSDM.1981.A-2-3

1981 Conference on Solid State Devices

Aug 26, 1981 - Aug 27, 1981
The Tokyo Chamber of Commerce and Industry, Tokyo, Japan

[A-2-3] A Low Power 8 Bit Parallel A/D Converter with High Accuracy Process

T. Takemoto, M. Inoue, H. Sadamatsu, A. Matsuzawa, Y. Hirofuji, T. Komeda (1.Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.)

https://doi.org/10.7567/SSDM.1981.A-2-3

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