[A-4-7] Josephson Cell Array Circuit Using Four Junction Logic (4 JL) Gates Hiroshi NAKAGAWA、Hideo OHIGASHI、Itaru KUROSAWA、Eiichi SOGAWA、Susumu TAKADA、Hisao HAYAKAWA (1.Electrotechnicaｌ Laboratory) https://doi.org/10.7567/SSDM.1983.A-4-7
