A 4x4 Bit Parallel Multiplier with GaAs JFET DCFL

Y. Kato; J. Kasahara; M. Wada; K. Taira; M. Dohsen; M. Arai; K. Gonoi; M. Sato; T. Hashimoto; N. Watanabe

doi:https://doi.org/10.7567/SSDM.1983.B-2-2

1983 Conference on Solid State Devices and Materials

1983年8月30日〜 1983年9月1日
The Tokyo Chamber of Commerce and Industry, Tokyo, Japan

[B-2-2] A 4x4 Bit Parallel Multiplier with GaAs JFET DCFL

Y. Kato、J. Kasahara、M. Wada、K. Taira、M. Dohsen、M. Arai、K. Gonoi、M. Sato、T. Hashimoto、N. Watanabe (1.Sony Corporation Research Center、2.Sony Corporation Semiconductor Group)

https://doi.org/10.7567/SSDM.1983.B-2-2

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