[A-2-5] Effect of Grain Boundaries on the I-V Characteristics of P-Channel MOSFET/SOI

T. Nishimura, K. Sugahara, S. Kusunoki, Y. Akasaka (1.LSI Research and Development Laboratory Mitsubishi Electric Corporation)

https://doi.org/10.7567/SSDM.1985.A-2-5