[B-7-4] An EPROM Cell Structure for EPLDs Compatible with Single Poly Gate Process
Kuniyoshi YOSHIKAWA、Seiichi MORI、Norihisa ARAI
(1.Semiconductor Device Engineering Laboratory, Toshiba Corporation、2.Toshiba Microcomputor Engineering Corporation)
https://doi.org/10.7567/SSDM.1986.B-7-4