A 5.4μm2 Sheath-Plate-Capacitor DRAM Cell with Self-Aligned Storage-Node Insulation

T. Kaga; Y. Kawamoto; T. Kure; Y. Nakagome; M. Aoki; T. Makino; H. Sunami

doi:https://doi.org/10.7567/SSDM.1987.A-1-2

[A-1-2] A 5.4μm2 Sheath-Plate-Capacitor DRAM Cell with Self-Aligned Storage-Node Insulation

T. Kaga, Y. Kawamoto, T. Kure, Y. Nakagome, M. Aoki, T. Makino, H. Sunami (1.Central Research Laboratory, Hitachi Ltd., 2.Hitachi VLSI Engineering Corp.)

https://doi.org/10.7567/SSDM.1987.A-1-2

1987 Conference on Solid State Devices and Materials

[A-1-2] A 5.4μm2 Sheath-Plate-Capacitor DRAM Cell with Self-Aligned Storage-Node Insulation