[A-1-3] A 5.4μm2 Stacked Capacitor DRAM Cell with 0.6μm Quadruple-Polysilicon Gate Technology
S. Kimura, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, M. Aoki, T. Kisu, H. Sunami
(1.Central Research Laboratory, Hitachi Ltd., 2.Hitachi VLSI Engineering Corp.)
https://doi.org/10.7567/SSDM.1987.A-1-3