[A-1-4] MeV-Boron Implanted Buried Barrier for Soft Error Reduction in Megabit DRAM

Y. Matsuda, K. Tsukamoto, M. Inuishi, M. Shimizu, M. Asakura, K. Fujishima, J. Komori, Y. Akasaka (1.LSI R&D Lab. Mitsubishi Electric Corp.)

https://doi.org/10.7567/SSDM.1987.A-1-4