[S-II-11] Lift-off Planarization Process for Josephson IC Multilevel Interconnections

Ichiro ISHIDA, Syuuichi TAHARA, Yumi AJISWA, Yoshifusa WADA (1.Microelectronics Res. Labs., NEC Corporation)

https://doi.org/10.7567/SSDM.1987.S-II-11