Nanometer Structure of Gate Electrode/Gate Insulator Interface and Anomalous Voltage Deviation of Tunneling Current in Submicron MOS Devices

M. Ushiyama; Y. Ohji; T. Nishimoto; K. Komori; H. Kume; S. Nakagawa; S. Tachi

doi:https://doi.org/10.7567/SSDM.1990.C-5-3

[C-5-3] Nanometer Structure of Gate Electrode/Gate Insulator Interface and Anomalous Voltage Deviation of Tunneling Current in Submicron MOS Devices

M. Ushiyama, Y. Ohji, T. Nishimoto, K. Komori, H. Kume, S. Nakagawa, S. Tachi (1.Central Research Laboratory, Hitachi Ltd., 2.Semiconductor Design & Development Center, Hitachi Ltd.)

https://doi.org/10.7567/SSDM.1990.C-5-3

1990 International Conference on Solid State Devices and Materials

[C-5-3] Nanometer Structure of Gate Electrode/Gate Insulator Interface and Anomalous Voltage Deviation of Tunneling Current in Submicron MOS Devices