Simulation of Tunneling Current due to Enhanced Electric Fields at the Edge of Gate Electrode

Hirotaka Muto; Hiroyoshi Kitabayashi; Koichiro Nakanishi Setsuo Wake; Moriyoshi Nakajima

doi:https://doi.org/10.7567/SSDM.1993.C-1-4

[C-1-4] Simulation of Tunneling Current due to Enhanced Electric Fields at the Edge of Gate Electrode

Hirotaka Muto、Hiroyoshi Kitabayashi、Koichiro Nakanishi Setsuo Wake、Moriyoshi Nakajima (1.Manufacturing Development Lab.、2.Kita-Itami Works Mitsubishi Electric Corp.)

https://doi.org/10.7567/SSDM.1993.C-1-4

1993 International Conference on Solid State Devices and Materials

[C-1-4] Simulation of Tunneling Current due to Enhanced Electric Fields at the Edge of Gate Electrode