A Low Parasitic Capacitance Scheme by Thermally Stable Titanium Silicide Technology for High Speed CMOS

[PC-1-20] A Low Parasitic Capacitance Scheme by Thermally Stable Titanium Silicide Technology for High Speed CMOS

Takehito Yoshida, Shinichi Ogawa, Akio Miyajima, Kousaku Yano (1.Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd.)