[A-9-2] Mechanism of Defect Formation during Low Temperature Si Epitaxy on Clean Si Substrate

I. Mizushima, M. Koike, T. Sato, K. Miyano, Y. Tsunashima (1.Microelectronics Engineering Laboratory, R&D Center Toshiba Corporation)

https://doi.org/10.7567/SSDM.1998.A-9-2