[B-1-5] An Analytical Delay Model for Read Operation at Any Position on DRAM Bit Lines

Hongchin Lin、Chia-Hsiang Sha、Shyh-Chyi Wong (1.Dept. of Electrical Engineering, National Chung-Hsing University、2.Institute of Electrical Engineering, Feng-Chia University)

https://doi.org/10.7567/SSDM.1998.B-1-5