An Ultra-Low Power Expandable 4-bit Adder/Subtracter IC Using Adiabatic Dynamic CMOS Logic Circuit Technology

Kazukiyo Takahashi; Koichi Ikeda; Mitsuru Mizunuma

doi:https://doi.org/10.7567/SSDM.1999.E-4-2

1999 International Conference on Solid State Devices and Materials

Sep 21, 1999 - Sep 24, 1999
Nihon Toshi Center Kaikan, Tokyo, Japan

[E-4-2] An Ultra-Low Power Expandable 4-bit Adder/Subtracter IC Using Adiabatic Dynamic CMOS Logic Circuit Technology

Kazukiyo Takahashi, Koichi Ikeda, Mitsuru Mizunuma (1.Yamagata University, Faculty of Engineering, Department of Electrical and Information Engineering)

https://doi.org/10.7567/SSDM.1999.E-4-2

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