[A-6-2] Etch Damage of n+Poly-Si Gate Side Wall as Evaluated by Gate Tunnel Leakage Current

H. MURAKAMI, T. MIHARA, S. MIYAZAKI, M. HIROSE (1.Department of Electrical Engineering, Hiroshima University)

https://doi.org/10.7567/SSDM.2000.A-6-2