Self-Aligned Pocket Implantation into Elevated Source/Drain MOSFETs for Reduction of Junction Capacitance and Leakage Current

Naruhisa Miura; Yuji Abe; Kohei Sugihara; Toshiyuki Oishi; Taisuke Furukawa; Takumi Nakahata; Katsuomi Shiozawa; Shigemitsu Maruno; Yasunori Tokuda

doi:https://doi.org/10.7567/SSDM.2000.B-1-7

[B-1-7] Self-Aligned Pocket Implantation into Elevated Source/Drain MOSFETs for Reduction of Junction Capacitance and Leakage Current

Naruhisa Miura、Yuji Abe、Kohei Sugihara、Toshiyuki Oishi、Taisuke Furukawa、Takumi Nakahata、Katsuomi Shiozawa、Shigemitsu Maruno、Yasunori Tokuda (1.Advanced Technology R&D Center, Mitsubishi Electric Corporation)

https://doi.org/10.7567/SSDM.2000.B-1-7

2000 International Conference on Solid State Devices and Materials

[B-1-7] Self-Aligned Pocket Implantation into Elevated Source/Drain MOSFETs for Reduction of Junction Capacitance and Leakage Current