Impact of Strained-Si Channel on CMOS Circuit Performance under the Sub-100nm Regime

Tetsuo Hatakeyama; Kazuya Matsuzawa; Shin-ichi Takagi

doi:https://doi.org/10.7567/SSDM.2000.B-2-4

2000 International Conference on Solid State Devices and Materials

2000年8月29日〜 2000年8月31日
Sendai International Center, Sendai, Japan

[B-2-4] Impact of Strained-Si Channel on CMOS Circuit Performance under the Sub-100nm Regime

Tetsuo Hatakeyama、Kazuya Matsuzawa、Shin-ichi Takagi (1.Advanced LSI Technology Laboratory, Corporate Research & Development Center, Toshiba Corporation)

https://doi.org/10.7567/SSDM.2000.B-2-4

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