Impact of Strained-Si Channel on CMOS Circuit Performance under the Sub-100nm Regime

Tetsuo Hatakeyama; Kazuya Matsuzawa; Shin-ichi Takagi

doi:https://doi.org/10.7567/SSDM.2000.B-2-4

2000 International Conference on Solid State Devices and Materials

Aug 29, 2000 - Aug 31, 2000
Sendai International Center, Sendai, Japan

[B-2-4] Impact of Strained-Si Channel on CMOS Circuit Performance under the Sub-100nm Regime

Tetsuo Hatakeyama, Kazuya Matsuzawa, Shin-ichi Takagi (1.Advanced LSI Technology Laboratory, Corporate Research & Development Center, Toshiba Corporation)

https://doi.org/10.7567/SSDM.2000.B-2-4

▲