[C-8-5] Proposal of a Partial-Ground-Plane(PGP) Silicon-on-Insulator(SOI) MOSFET for Deep Sub-100-nm Channel Regime

Shin-ichiro Yanagi、Atsushi Nakakubo、Yasuhisa Omura (1.High-Tech. Research Center and Faculty of Eng., Kansai University)

https://doi.org/10.7567/SSDM.2000.C-8-5