[A-2-2] Modeling and Analysis of Gate Line Edge Roughness Effect on CMOS Scaling Towards Deep Nanoscale Gate Length

Seong-Dong Kim, Sungkwon Hong, Jae-Kwan Park, Jason C. S. Woo (1.Department of Electrical Engineering, University of California)

https://doi.org/10.7567/SSDM.2002.A-2-2