Methodology for Accurate C-V Measurement of Gate Insulators below 1.5nm EOT

Hiroyuki Suto; Yasushi Okawa; Mariko Takayanagi; Hideyuki Norimatsu; Yoshiaki Toyoshima

doi:https://doi.org/10.7567/SSDM.2002.C-7-1

[C-7-1] Methodology for Accurate C-V Measurement of Gate Insulators below 1.5nm EOT

Hiroyuki Suto、Yasushi Okawa、Mariko Takayanagi、Hideyuki Norimatsu、Yoshiaki Toyoshima (1.SoC Research and Development Center, Toshiba Corporation Semiconductor Company、2.Hachioji Semiconductor Test Division, Agilent Technologies Japan, Ltd.)

https://doi.org/10.7567/SSDM.2002.C-7-1

2002 International Conference on Solid State Devices and Materials

[C-7-1] Methodology for Accurate C-V Measurement of Gate Insulators below 1.5nm EOT