[A-2-5] Eliminating Threshold Voltage Offset of PMOSFETs in High-Density DRAM
Norikatsu Takaura, Riichiro Takemura, Hideyuki Matsuoka, Ryo Nagai, Satoru Yamada, Hisao Asakura, Shin’ichiro Kimura
(1.Central Research Laboratory, Hitachi, Ltd., 2.Advanced Device Development Gr., Elpida Memory, Inc., 3.Information & Control System Division, Computer Systems Quality Assurance Sect, Hitachi, Ltd.)
https://doi.org/10.7567/SSDM.2003.A-2-5
