Channel direction impact of (110) surface Si substrate on performance improvement in sub-100 nm MOSFETs

Hidetatsu Nakamura; Tatsuya Ezaki; Toshiyuki Iwamoto; Mitsuhiro Togo; Nobuyuki Ikarashi; Masami Hane; Toyoji Yamamoto

doi:https://doi.org/10.7567/SSDM.2003.A-9-2

2003 International Conference on Solid State Devices and Materials

Sep 16, 2003 - Sep 18, 2003
Keio Plaza Inter-Continental Tokyo (Keio Plaza Hotel), Tokyo, Japan

[A-9-2] Channel direction impact of (110) surface Si substrate on performance improvement in sub-100 nm MOSFETs

Hidetatsu Nakamura, Tatsuya Ezaki, Toshiyuki Iwamoto, Mitsuhiro Togo, Nobuyuki Ikarashi, Masami Hane, Toyoji Yamamoto (1.Silicon Systems Research Labs., NEC Corporation)

https://doi.org/10.7567/SSDM.2003.A-9-2

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