Low-Noise and High-Frequency 0.10μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Network LSI

Toshiaki Iwamatsu; Mikio Tujiuchi; Yuuichi Hirano; Takuji Matsumoto; Hiroyuki Takashino; Tatsuhiko Ikeda; Tsutomu Yoshimura; Daniel Chen; Toshihide Oka; Harufusa Kondoh; Takashi Ipposhi; Shigeto Maegawa; Yasuo Inoue; Masahide Inuishi; Yuzuru Ohji

doi:https://doi.org/10.7567/SSDM.2003.B-10-2

[B-10-2] Low-Noise and High-Frequency 0.10μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Network LSI

Toshiaki Iwamatsu、Mikio Tujiuchi、Yuuichi Hirano、Takuji Matsumoto、Hiroyuki Takashino、Tatsuhiko Ikeda、Tsutomu Yoshimura、Daniel Chen、Toshihide Oka、Harufusa Kondoh、Takashi Ipposhi、Shigeto Maegawa、Yasuo Inoue、Masahide Inuishi、Yuzuru Ohji (1.Advanced Device Development Dept., Renesas Technology Corp.、2.High Frequency & Optical Semiconductor Division, Mitsubishi Electric Corporation)

https://doi.org/10.7567/SSDM.2003.B-10-2

2003 International Conference on Solid State Devices and Materials

[B-10-2] Low-Noise and High-Frequency 0.10μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Network LSI