[B-7-1] Low Tinv (≤ 1.8 nm) Metal-Gated MOSFETs on SiO2 Based Gate Dielectrics for High Performance Logic Applications

V. Ku, R. Amos, A. Steegen, C. Cabral, Jr., V. Narayanan, P. Jamison, P. Nguyen, Y. Li, M. Gribelyuk, Y. Wang, J. Cai, A. Callegari, F. McFeely, F. Jamin, K. Wong, E. Wu, A. Chou, D. Boyd, H. Ng, M. Ieong, C. Wann, R. Jammy, W. Haensch (1.IBM Semiconductor Research and Development Center, 2.IBM T.J. Watson Research Center)

https://doi.org/10.7567/SSDM.2003.B-7-1