[D-5-4] P-channel Vertical Double-Gate MOSFET Fabrication by Ion-Bombardment-Retarded Etching

Meishoku Masahara、Takashi Matsukawa、Shinichi Hosokawa、Kenichi Ishii、Yongxun Liu、Hisao Tanoue、Kunihiro Sakamoto、Hiromi Yamauchi、Seigo Kanemaru、Eiichi Suzuki (1.Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST))

https://doi.org/10.7567/SSDM.2003.D-5-4