Neutral Beam Etching for Damage-free 50 nm Gate Electrode Patterning

Shuichi Noda; Hirotomo Nishimori; Tohru Ida; Tsunetoshi Arikado; Katsunori Ichiki; Seiji Samukawa

doi:https://doi.org/10.7567/SSDM.2003.P3-12

2003 International Conference on Solid State Devices and Materials

Sep 16, 2003 - Sep 18, 2003
Keio Plaza Inter-Continental Tokyo (Keio Plaza Hotel), Tokyo, Japan

[P3-12] Neutral Beam Etching for Damage-free 50 nm Gate Electrode Patterning

Shuichi Noda, Hirotomo Nishimori, Tohru Ida, Tsunetoshi Arikado, Katsunori Ichiki, Seiji Samukawa (1.Institute of Fluid Science, Tohoku University, 2.Semiconductor Leading Edge Technologies, Inc. (Selete), 3.Ebara Research Co., Ltd.)

https://doi.org/10.7567/SSDM.2003.P3-12

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