An Integrated Gate Stack Process for Sub-90nm CMOS Technology

S. J. Chang; S. Y. Wu; C. L Chen; T. L Lee; Y. M. Lin; Y. S. Tsai; H. D. Su; S. B. Chen; Y. S Chen; M. S. Liang; Y. C. See; Y. C. Sun

doi:https://doi.org/10.7567/SSDM.2003.P3-6

2003 International Conference on Solid State Devices and Materials

Sep 16, 2003 - Sep 18, 2003
Keio Plaza Inter-Continental Tokyo (Keio Plaza Hotel), Tokyo, Japan

[P3-6] An Integrated Gate Stack Process for Sub-90nm CMOS Technology

S. J. Chang, S. Y. Wu, C. L Chen, T. L Lee, Y. M. Lin, Y. S. Tsai, H. D. Su, S. B. Chen, Y. S Chen, M. S. Liang, Y. C. See, Y. C. Sun (1.Taiwan Semiconductor Manufacturing Company)

https://doi.org/10.7567/SSDM.2003.P3-6

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