Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond

T. Hayashi; T. Yamashita; K. Shiga; K. Hayashi; H. Oda; T. Eimori; M. Inuishi; Y. Ohji

doi:https://doi.org/10.7567/SSDM.2004.A-1-3

[A-1-3] Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond

T. Hayashi、T. Yamashita、K. Shiga、K. Hayashi、H. Oda、T. Eimori、M. Inuishi、Y. Ohji (1.Renesas Technology Corp., Wafer Process Engineering Development Dept.)

https://doi.org/10.7567/SSDM.2004.A-1-3

2004 International Conference on Solid State Devices and Materials

[A-1-3] Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond