[A-1-5] Strained-Si for CMOS 65nm node : Si0.8Ge0.2 SRB or “Low Cost” approach ?

F. Boeuf, F. Payet, N. Casanova, Y. Campidelli, N. Villani, O. Kermarrec, J.M. Hartmann, N. Emonet, F. Leverd, P. Morin, C. Perrot, V. Carron, C. Laviron, F. Arnaud, S. Jullian, D. Bensahel, T. Skotnicki (1.STMicroelectronics, 2.CEA-LETI, 3.Philips Semiconductors)

https://doi.org/10.7567/SSDM.2004.A-1-5