[B-10-3] Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications

M. Vinet, T. Poiroux, J. Widiez, J. Lolivier, B. Previtali, C. Vizioz, B. Guillaumot, P. Besson, J. Simon, F. Martin, S. Maitrejean, P. Holliger, B. Biasse, M. Casse, F. Allain, A. Toffoli, D. Lafond, J.M. Hartmann, R. Truche, V. Carron, F. Laugier, A. Roman, Y. Morand, D. Renaud, M. Mouis, S. Deleonibus (1.CEA/DRT-LETI, 2.STMicroelectronics, 3.IMEP (UMR CNRS/INPG/UJF))

https://doi.org/10.7567/SSDM.2004.B-10-3